1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a counter circuit.
2. Description of the Background Art
A semiconductor device operating in synchronization with an externally applied clock contains, in many cases, a counter circuit for frequency-dividing the applied external clock. There are various kinds of counters. The most common one is a binary counter which can represent the state of two to n-th power with n latches. A binary counter is such a counter in that outputs of n latches correspond to respective bits, which respectively correspond to 20 to 2n.
In a binary counter, however, operational frequency is limited, since critical path exists from the establishment of lower bits to the establishment of upper bits. Further, in such an application in that pulse signals are output at every certain period, output of each bit needs to be decoded by an AND circuit to be used. A pulse signal generated by such decoding must be once received by D flip-flop, in order to use the signal as an internal clock signal serving as a reference of operation.
Recently, as the speed of operation of a semiconductor device has increased, in some cases, an external clock is multiplied internally to generate a faster internal clock so that an operation is performed in synchronization therewith. In an application that requires such a high-speed operation, a ring counter which can operate faster than a binary counter may be used. A ring counter is used as a frequency divider of the clock or for creating a timing signal serving as an operational reference of an internal circuit.
A ring counter is a counter in which bistable units such as flip-flops are connected in a loop. At any given time, only one flip-flop holds xe2x80x9cHxe2x80x9d (high) data while the remaining flip-flops hold xe2x80x9cLxe2x80x9d (low) data. Each time clock signal is counted, the position of the flip-flop holding xe2x80x9cHxe2x80x9d data successively circulates around the loop.
FIG. 8 is a block diagram showing a schematic configuration of a conventional semiconductor device 452.
Referring to FIG. 8, semiconductor device 452 includes: an internal clock generating circuit 454 receiving an externally applied clock signal CLK and a reset signal /RESET and outputting an internal clock signal at a frequency n-times that of external clock signal CLK; and an internal circuit 456 receiving an externally applied input signal DIN, operating in synchronization with internal clock signal ICLK and outputting an output signal DOUT to the external.
Internal clock generating circuit 454 includes: a PLL (Phase Locked Loop) circuit 458 receiving a clock signal CLK and outputting internal clock signal ICLK; and a ring counter 500 starting an operation after initialized by externally applied reset signal /RESET and frequency-dividing internal clock signal ICLK to output an internal clock signal RCLK. Internal clock signal RCLK has a frequency that is one-nth of clock signal ICLK. Internal clock signal RCLK is compared in phase with externally applied clock signal CLK by PLL circuit 458.
FIG. 9 is a circuit diagram showing a configuration of ring counter 500 shown in FIG. 8.
Referring to FIG. 9, ring counter 500 includes a gate circuit 502#1 receiving internal clock signal RCLK and reset signal /RESET.
Gate circuit 502#1 has its output driven to H level when reset signal /RESET is activated to L level, and driven to H level when internal clock signal RCLK is set to H level.
Ring counter 500 further includes: a D flip-flop 504#1 receiving an output of gate circuit 502#1 in synchronization with internal clock signal ICLK; an AND circuit 502#2 receiving an output of D flip-flop 504#1 and reset signal /RESET; and a D flip-flop 504#2 receiving an output of AND circuit 502#2 in synchronization with internal clock signal ICLK.
Ring counter 500 further includes: an AND circuit 502#3 receiving an output of D flip-flop 504#2 and reset signal /RESET; a D flip-flop 504#3 receiving an output of AND circuit 502#3 in synchronization with internal clock signal ICLK; an AND circuit 502#4 receiving an output of D flip-flop 504#3 and reset signal /RESET; and a D flip-flop 504#4 receiving an output of AND circuit 502#4 in synchronization with internal clock signal ICLK.
Ring counter 500 further includes: an AND circuit 502#5 receiving an output of D flip-flop 504#4 and reset signal /RESET; a D flip-flop 504#5 receiving an output of AND circuit 502#5 in synchronization with internal clock signal ICLK; an AND circuit 502#6 receiving an output of D flip-flop 504#5 and reset signal /RESET; and a D flip-flop 504#6 receiving an output of AND circuit 502#6 in synchronization with internal clock signal ICLK.
Ring counter 500 further includes: an AND circuit 502#7 receiving an output of D flip-flop 504#6 and reset signal /RESET; a D flip-flop 504#7 receiving an output of AND circuit 502#7 in synchronization with internal clock signal ICLK; an AND circuit 502#8 receiving an output of D flip-flop 504#7 and reset signal /RESET; and a D flip-flop 504#8 receiving an output of AND circuit 502#8 in synchronization with internal clock signal ICLK.
An output of D flip-flop 504#8 is provided to PLL circuit 458 in FIG. 8 as internal clock signal RCLK, and compared in phase with clock signal CLK.
FIG. 10 is an operational waveform diagram illustrating an operation of ring counter 500 shown in FIG. 9.
Referring to FIGS. 9 and 10, Q1-Q8 are output signals of D flip-flops 504#1-504#8, respectively. Firstly, in clock cycle #1, signal Q1 is at H level and signals Q2-Q8 are at L level. Then, in clock cycle #2, signal Q1 falls to L level in response to a rise of internal clock signal ICLK and instead of signal Q1, signal Q2 rises to H level. Signals Q3-Q8 remain at the state of L level.
Afterwards, at every rising edge of the clock signal, the flip-flop outputting H level shifts to the latter stage one by one. When clock cycle #8 terminates, again in clock cycle #9, signal Q1 is returned to be at H level and signals Q2-Q8 to be at L level. Such a ring counter in that shift registers are connected in a ring enables a high-speed operation, and in addition, the output signal of flip-flop 504#8 can be directly used as a timing reference signal.
As explained above, among flip-flops constituting a shift register, only one flip-flop holds H data which is transmitted to the next stage every time internal clock signal ICLK is input. Therefore, when internal clock signal ICLK corresponding to the number of flip-flops. is received, a reference pulse signal can be obtained which has a period corresponding to the number of flip-flops in one clock width as internal clock signal RCLK. By changing the number of flip-flops, in such a ring counter, the period of output signal can be changed easily.
However, ring counter as such has a problem, that is, once an error occurs, it cannot recover from the error until a reset signal is input again.
FIG. 11 is a waveform diagram illustrating an error of a conventional ring counter.
Referring to FIGS. 9 and 11, signals Q1-Q8 show outputs signals of D flip-flops 504#1-504#8, respectively.
In clock cycles #1-#4, the position of D flip-flop outputting H level successively is shifting in order, similar to the operation explained with respect to FIG. 10.
In clock cycle #5, the output node of D flip-flop 504#1 suffers noise of H level caused, for example, by radiation and the like and that noise may be held.
Then, in clock cycle #6, H data due to the noise is shifted to the next stage, resulting in signal Q2 driven to H level. Therefore, after clock cycle #6, two flip-flops out of eight hold H level data.
For example, in clock cycle #8, signals Q4 and Q8 are brought to be at H level. Thus, after clock cycle #8, internal clock signal RCLK output from ring counter 500 comes to have a frequency twice that of the original one. As a result, PLL circuit 458 in FIG. 8 causes an error in which it generates a clock signal with the frequency reduced to one half that of an internal clock signal to be generated.
More specifically, though ring counter 500 shown in FIG. 9 can represent the states in only eight ways in normal operation, it can represent the states in 256 ways as a combination. Therefore, there arises a problem in which when the ring counter goes into any of the states of the combination in 248 ways as the abnormal state, it cannot recover to its normal operation. For example, in such an application that is continuously run for a long time and cannot be initialized by power-on, such as a workstation operating all night, an air-conditioner for controlling the temperature in a plant, a security system, a internet server and the like, the occurrence of such an error results in a big problem.
An object of the present invention is to provide a reliable semiconductor device which is able to recover to a normal state immediately even if an error occurs.
The present invention, in summary, provides a semiconductor device including a plurality of holding circuits and a reset circuit.
The plurality of holding circuits are connected in series in a ring, each receives data in synchronization with a clock signal and transmits it to the next stage. The reset circuit monitors hold data in the plurality of holding circuits, and when detecting an abnormal state, initializes the hold data. The reset circuit initializes the hold data when data of a first logical value exists in a first portion of the plurality of holding circuits and data of the first logical value exists in a second portion excluding the first portion of the plurality of holding circuits, or when data of the first logical value does not exist in the first portion of the plurality of holding circuits and data of the first logical value does not exist in the second portion excluding the first portion of the plurality of holding circuits.
According to another aspect of the present invention, the present invention provides a semiconductor device including a plurality of holding circuits and a reset circuit.
The plurality of holding circuits are connected in series in a ring, each receives data in synchronization with a clock signal and transmits it to the next stage. The reset circuit monitors hold data in the plurality of holding circuits, and when detecting an abnormal state, initializes the hold data. The reset circuit includes: a plurality of decode circuits detecting a plurality of states, respectively, which the plurality of holding circuits may take in a normal operational state; and an output circuit outputting a reset signal for initializing the hold data when none of outputs of the plurality of decode circuits are activated.
Therefore, a main advantage of the present invention is that it enhances an operational reliability because of the capability to recover from an erroneous state to the normal operational state even when an error is caused by noise of radiation and the like.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.